1. Field of the Invention
The present invention relates to the fabrication of semiconductor structures, and more particularly, to the formation of damascene interconnects through the creation of platinum seed layers to selectively plate copper in the manufacture of integrated circuits.
2. Description of the Prior Art
As integrated circuit feature sizes continue to decrease, it has become advantageous to construct metal connections out of copper instead of aluminum. Copper has a lower resistivity than aluminum, and therefore can form higher speed connections for a given line width.
The disadvantage of copper, however, is that it is more difficult to reliably etch than aluminum. To create copper traces, therefore, alternative design approaches such as damascene and dual damascene structures have been employed. By using damascene techniques, copper line etches are eliminated. Instead, trenches are first cut into the isolation dielectric material where connective traces are planned. Then the copper is deposited to fill the traces. A polishing process is used to etch back any overfill of copper in the trenches. In this way, damascene approaches allow the use of copper for interconnects.
Referring to FIG. 1, a cross-section of a partially completed prior art dual damascene structure is shown. A substrate layer 10 is depicted. The substrate layer 10 encompasses all underlying layers, devices, junctions, and other features that have been formed prior to the deposition and definition of the conductive traces 18 in the isolation layer 14. A dielectric layer 22 overlies the isolation layer 26 and partially overlies the conductive traces 18.
A via opening is shown formed in the dielectric layer 22 to expose the top surface of the conductive trace 18. A trench is also formed in the dielectric layer 22. A barrier layer 30 is deposited overlying the dielectric layer 22 and the exposed conductive traces 18. The purpose of the barrier layer 30 is to prevent diffusion of the subsequently deposited copper into the conductive traces 18 or the dielectric layer 22. Since the copper layer will be deposited using electroless plating, a seed layer 34 is deposited overlying the barrier layer 30. The purpose of the seed layer 34 is to provide a thin layer of activation atoms to catalyze the electroless plating process. The seed layer 34 may be made up of copper, platinum, or palladium. The seed layer 34 is typically deposited by a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process.
Referring to FIG. 2, the result of the electroless plating deposition of the copper layer 38 is shown. Assuming copper was used as the seed layer 34, the seed layer 34 is absorbed into the copper layer 38 during the deposition process. Note that the copper layer 38 is deposited everywhere on the wafer overlying the barrier layer 30. This universal deposition of the copper layer 38 is because the seed layer 34 was also deposited everywhere on the wafer. To form interconnect elements, both the excess copper layer 38 and the excess barrier layer 30 must be removed. This is typically accomplished by subjecting the wafers to a chemical mechanical polish (CMP).
Referring now to FIG. 3, during the CMP process, the copper layer 38 is polished down to a plug. An encapsulation layer 42 is deposited overlying the copper layer 38 to protect the copper from oxidation during subsequent processing steps.
It would be advantageous to eliminate the CMP process used to polish down the copper layer 38 in the prior art method. To do this, it is helpful to deposit the copper only where it is needed. Likewise, it would be advantageous to simplify, and make less expensive, the process used to form the seed layer 34.
Several prior art approaches attempt to improve electroless plating processes for use in integrated circuit metalization. U.S. Pat. No. 5,674,787 to Zhao et al teaches a process to selectively deposit copper to form interconnect plugs. A copper ion seed layer is used to activate the electroless copper plating process. A dielectric layer is deposited and anisotropically etched to form a dielectric barrier on the sidewalls of the connective trench. An encapsulation layer is electroless plated over the copper plug. U.S. Pat. No. 5,723,387 to Chen discloses an apparatus and a process for forming copper interconnects. Platinum or palladium ions are used as the seed layer to activate the electroless plating of the copper layer. The copper layer is not selectively deposited and a post plating chemical mechanical polish must be done. U.S. Pat. No. 4,574,095 to Baum et al teaches a process to selectively deposit copper by formation of a palladium seed layer by photo-induced decomposition of gaseous complex at a wavelength of 249 nanometers. The electroless plated copper layer is then deposited where the palladium layer is so formed. U.S. Pat. No. 5,824,599 to Schacham-Diamond et al teaches a process to non-selectively deposit a copper layer by electroless plating. An aluminum layer is deposited overlying the copper seed layer to prevent oxidation of the seed layer prior to plating. U.S. Pat. No. 5,308,796 to Feldman et al discloses a process to selectively deposit a copper layer over a metal silicide layer. U.S. Pat. No. 4,692,349 to Georgiou et al discloses a process to electroless plate cobalt or nickel to form via plugs.